module FIR_APP(
    input clk_60m,
    input rst_n,
    input signed [15:0] data_l,
    input signed [15:0] data_r,
    input data_async,
    input data_valid,
    output reg signed [23:0] AF_data_l,
    output reg signed [23:0] AF_data_r
);
//1.输入数据总线
wire signed [15:0] data;
assign data = (data_async & data_valid) ? data_l : data_r; //两者都为1时为通道一(左)，反之为通道二(右)

//2.例化模块
Advanced_FIR_Filter_Top your_instance_name(
		.clk(clk_60m), //input clk
		.rstn(rst_n), //input rstn
		.fir_rfi_o(     ), //output fir_rfi_o
		.fir_valid_i(data_valid), //input fir_valid_i
		.fir_sync_i(data_async), //input fir_sync_i
		.fir_data_i(data), //input [15:0] fir_data_i
		.fir_valid_o(fir_valid_o_o), //output fir_valid_o
		.fir_sync_o(fir_sync_o_o), //output fir_sync_o
		.fir_data_o(fir_data_o_o) //output [30:0] fir_data_o
);
//3.输出信号
wire fir_valid_o_o;
wire fir_sync_o_o;
wire [30:0] fir_data_o_o;
always @(posedge clk_60m or negedge rst_n) begin
    if(!rst_n) begin
        AF_data_l <= 24'd0;
        AF_data_r <= 24'd0;
    end
    else if(fir_valid_o_o && fir_sync_o_o) begin //左声道数据
        AF_data_l <= fir_data_o_o[30 : 7];
        AF_data_r <= AF_data_r;
    end
    else if(fir_valid_o_o && ~fir_sync_o_o) begin //右声道数据
        AF_data_l <= AF_data_l;
        AF_data_r <= fir_data_o_o[30 : 7];
    end
    else begin
        AF_data_l <= AF_data_l;
        AF_data_r <= AF_data_r;
    end
end

endmodule
